1. Field of the Invention
The present invention relates to a semiconductor apparatus provided with a trench gate structure, and the fabrication method thereof.
Priority is claimed on Japanese Patent Application No. 2007-151597, filed Jun. 7, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
A semiconductor apparatus generally has a structure where an n-type diffusion layer, a gate insulating film, and a gate electrode are formed on the surface of a semiconductor substrate. However, as further refinement of the ultra large scale integration (ULSI) device is taking place, the problem of a short channel effect is becoming apparent.
The short channel effect refers to the following phenomenon. When a source electrode and a drain electrode become close as the gate length shortens, a leakage current flows between the source and drain (punch through) even if the gate is closed since silicon is a semiconductor with relatively high conductivity.
As a means for avoiding this short channel effect, trench gate technology has attracted attention. Trench gate technology refers to a method in which a trench is formed by engraving an Si substrate under a gate wiring and a gate is embedded in the trench, thereby enabling the elongation of channel length even with the same gate occupying area.
FIG. 16 shows a cross sectional structure of a semiconductor apparatus provided with such a conventional trench-embedded gate electrode.
In a semiconductor apparatus 101, a transistor structure T is formed between a pair of trench-type device isolation portions 102. Specifically, an n-type diffusion layer 104 to become a source region or a drain region is formed on the surface of a semiconductor substrate 103, which has a p-type well layer 103a and a channel doped layer 103b. In addition, a trench 105 is formed in the semiconductor substrate 103 and the n-type diffusion layer 104, and a source region and a drain region in the n-type diffusion layer 104 are divided by this trench 105. Moreover, a gate insulating film 106 is formed on the n-type diffusion layer 104, which includes the inner surface of the trench 105, and the device isolation portions 102. Additionally, a gate electrode 107 is embedded in the trench 105. The gate electrode 107 is embedded in the trench 105 via the gate insulating film 106. As described so far, the gate electrode 107 is formed between the source region and the drain region of the n-type diffusion layer 104 via the gate insulating film 106. In addition, electrodes 108 and 109 are formed on the source region and the drain region, respectively. Moreover, a silicon oxide film 110 is formed on the gate insulating film 106 and the electrodes 108 and 109 and the gate electrode 107 are disposed so as to be embedded in this silicon oxide film 110.
As described so far, according to the semiconductor apparatus 101 provided with a trench-embedded gate electrode by trench gate technology, by configuring the gate electrode 107 to be embedded in the trench 105, it is possible to control the effective channel length due to the trench depth and it is also possible to achieve a higher threshold voltage Vth compared to that achieved by conventional planar-type semiconductor apparatuses.
However, the following problem is associated with conventional trench gate technology. That is, when processing a trench 205 by a plasma etching operation as shown in FIG. 17 and forming the trench 205 with respect to an active region K, which is shown in FIG. 17(a) as oblong shaped in a planar view, in the step for forming the trench 205, an Si burr 103c is readily formed beside the device isolation portions 102 as shown in FIG. 17(c), and this Si burr 103c acts as a parasitic channel.
A chemical etching process or a hydrogen annealing treatment is known to alleviate the problem of this Si burr 103c. 
For example, Patent Document 1 (Japanese Unexamined Patent Application, First Publication No. 2001-351895) describes a method in which the trench shape is improved by the wet treatment using a mixed solution of hydrofluoric acid and nitric acid and the chemical etching process involving a short time heat treatment.
Additionally, Patent Documents 2 (Japanese Unexamined Patent Application, First Publication No. 2003-229479), 3 (Japanese Unexamined Patent Application, First Publication No. 2004-140039), and 4 (Japanese Unexamined Patent Application, First Publication No. 2005-142265) describe a method to flatten the inner wall of a trench by the hydrogen annealing treatment.
However, when the extent of Si burr is alleviated by subjecting the trench to an isotropic chemical etching process following a dry etching operation, a bottom portion 205b of the trench 205 will become round shaped as shown in FIGS. 18(b) and 18(c), and thus the effect of Si burr cannot be eliminated completely. Moreover, in the above case, cross sectional shape of the trench in the direction of A1-A1′ line in FIG. 18(a) will deteriorate due to the excessive side etching. Thereafter, as shown in FIG. 19, the trench 205 is formed by removing a mask. However, the cross sectional shape of the trench 205 will be substantially circular and the central portion thereof in the depth direction will be a rounded dent, and thus the trench upper portion 205a will have a shape projecting inward. Since a transistor is produced from this state, for example, a transistor 201 shown in FIG. 20 will be configured by embedding the gate electrode 207 in the trench 205 via the gate insulating film 206, on electric field concentration readily occurs at the trench upper portion 205a and the risk of dimensional change will also be great.
In addition, when a hydrogen baking process (a heat treatment in a hydrogen atmosphere at about 900° C.) is conducted, as shown in FIG. 18(d), the Si burr can be eliminated substantially completely making a bottom portion of the trench 305b flat. However, similar to the abovementioned case, cross sectional shape of the trench in the direction of A1-A1′ line will be substantially circular. Accordingly, when a transistor is produced as in the above case by removing a mask, an electric field concentration readily occurs at the trench upper portion and the risk of dimensional change will also be great.
The present invention is made in view of the above circumstances and its object is to provide a semiconductor apparatus and a fabrication method thereof in which the trench shape is optimized while efficiently removing the burr generated during the processing of the trench in the trench gate transistor, and in which a parasitic channel or a leakage current does not occur.